1. Field of the Invention
The present invention relates to a memory control apparatus, an information processing apparatus, and a memory control method.
2. Description of the Related Art
When printing process is performed with image data in PDL (Page Description Language) format, the image data in the PDL format are expanded into image data in a raster format (hereinafter referred to as “raster image data”), and the printing process is performed based on the raster image data. The processing for generating the raster image data from the image data in the PDL format is called RIP (Raster Image Processing) processing. An image forming system for performing high-speed processing for large-volume printing businesses is likely to employ a configuration in which a DFE (Digital Front End) apparatus for performing the RIP processing and an image forming apparatus for printing an image onto paper, which is a recording medium, based on raster image data are separately provided. In this case, the DFE apparatus and the image forming apparatus are connected via a communication cable and the like, and the RIP-processed raster image data are transferred from the DFE apparatus to the image forming apparatus via information communication based on, for example, PCI Express (hereinafter referred to as “PCIe”) standard.
In this kind of image forming system, a DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) capable of achieving high-speed data transfer speed is often used as memory for temporarily storing raster image data transferred from the DFE apparatus to the image forming apparatus. The DDR-SDRAM (hereinafter abbreviated as “DDR”) can exchange data both at the rising and the falling edges of a clock signal. Theoretically, the DDR provides a data transfer speed twice as fast as the data transfer speed of an SDRAM operating with the same clock.
Writing and reading of data to/from the DDR is achieved by access to a memory cell specified by two addresses, i.e., a row address and a column address. When the same row address is accessed successively at this occasion, writing and reading of data can be performed at a high speed. On the other hand, when a row address is switched frequently, and in particular, when data are written and read alternately by specifying different row addresses, it takes time to wait for completion of command reception every time writing and reading are switched, and this reduces the performance.
The above image forming system performs, in parallel, processing for transferring raster image data from the DFE apparatus to the image forming apparatus and writing the raster image data to the DDR and processing for printing an image based on the raster image data read from the DDR. Therefore, writing and reading of the raster image data to/from the DDR is alternately performed in a time division manner, and switching frequently occurs between writing and reading of data with different row addresses specified, and the data transfer efficiency is considered to decrease.
For example, a memory bandwidth control apparatus as described in Japanese Patent Application Laid-open No. 2005-84907 is known as a technique for improving the data transfer efficiency between an external device and memory. In this memory bandwidth control apparatus, an I/O buffer is provided to dynamically allocate a memory bandwidth for only an external device requesting data transfer among multiple external devices connected via an input/output port, and this can reduce useless consumption of the memory bandwidths as compared with a case where memory bandwidths are fixedly allocated to the multiple external devices, whereby the data transfer efficiency between the external devices and the memory is enhanced.
However, the technique described in Japanese Patent Application Laid-open No. 2005-84907 is a technique for improving the data transfer efficiency by allocating a memory bandwidth for only an external device requesting data transfer among the multiple external devices. Therefore, when the technique described in Japanese Patent Application Laid-open No. 2005-84907 is applied to the above image forming system, it is impossible to perform, in parallel, the processing for transferring the raster image data from the DFE apparatus to the image forming apparatus and writing the raster image data to the DDR and the processing for printing an image based on the raster image data read from the DDR, and this reduces the performance as the image forming system. When the transfer of the raster image data from the DFE apparatus to the image forming apparatus and the printing of the image based on the raster image data read from the DDR are performed in parallel, switching frequently occurs between writing and reading of data having different row addresses specified for the DDR even if the technique described in Japanese Patent Application Laid-open No. 2005-84907 is applied, and therefore, the data transfer efficiency is considered to decrease.